1. Field of the Invention
This invention relates to methods and systems for fast access of computer-based memories.
2. Related Art
Modern computer-based systems often use wide memories that have a constant width. However, these systems must often manipulate a variety of variables having different data widths. For instance, a particular processor can have a thirty-two bit (four byte) wide bus with a thirty-two bit-wide random access memory (RAM), but must manipulate any number of variables having eight bit (one byte), sixteen bit (two bytes) or thirty-two bit widths.
One problem that can arise with such systems is that data can become misaligned with the physical boundaries of the available memory. For example, a first variable in a block of thirty-two bit-wide RAM may be a byte-wide variable while a second variable may be a four-byte variable. As a result, the first variable will occupy the first byte of a first memory location, while the second variable will occupy the remaining three bytes of the first memory location plus the first byte of the next memory location. One unfortunate consequence of this situation is that a computer accessing the second variable can take two separate memory-access cycles to either read or write the second variable.
While various approaches are available to align various variables having different bit-widths with the address boundaries of a memory, these approaches typically require a wasteful use of available memory resources or otherwise cannot be used with practicable systems. Accordingly, new technologies that can eliminate multiple-cycle memory accesses for misaligned data are desirable.
The invention provides techniques directed to accessing misaligned data words in an array of memory cells. In various embodiments, techniques directed to reading a misaligned data variable are provided where a first portion of the misaligned data variable resides in one or more first memory cells associated with a first address and a second portion of the misaligned data variable resides in one or more second memory cells associated with a second address.
By contemporaneously providing first and second address-selection information as well as first and second read information, enabling circuits can read-enable one or more of the first memory cells based on the first address-selection and first read information, and further read-enable the one or more of the second memory cells based on the second address-selection information and second read information. The data from the enabled memory cells can then be received and assembled by a device, such as buffer circuitry, optionally shifted, then provided to an external device.
In various other embodiments, techniques directed to writing a misaligned data variables are provided where a first portion of the misaligned data variable is directed to one or more first memory cells associated with a first address and a second portion of the misaligned data variable is directed one or more second memory cells associated with a second address.
By contemporaneously providing first and second address-selection information as well as first and second write information, enabling circuits can write-enable one or more of the first memory cells based on the first address-selection and first write information, and further write-enable the one or more of the second memory cells based on the second address-selection information and second write information. Meanwhile, a device, such as buffer circuitry, can receive the misaligned data variable from an external source, appropriately shift the misaligned data variable and provide the shifted data of the misaligned data variable to the write-enabled memory cells of the two memory locations.
Accordingly, data access operations that would take two memory-access cycles on a conventional memory system are reduced to using a single memory-access cycle. Others features and advantages will become apparent in the following descriptions and accompanying figures.